1. Field of the Invention
The present invention generally relates to a method and circuit for shortcircuiting a pair of data transfer lines of a semiconductor memory device in which complementary data signals are transmitted over the pair of data transfer lines in order to write data in a memory cell array or read data therefrom.
A DRAM (Dynamic Random Access Memory) device is known as such a semiconductor memory device in which complementary read or write data signals are transmitted over a pair of transfer lines to which a plurality of rows of memory cells (such lines are referred to as global data transfer lines) are connected via local data transfer lines. Usually, such a pair of global data transfer lines, which functions as a global data bus, is connected together (shortcircuited) in order to precharge the pair of global data transfer lines and thus speed up the operation of the device. It is necessary to take into consideration a timing at which the pair of global data transfer lines is released from the precharged state. This consideration is important particularly for high-speed memory devices such as synchronous DRAM devices (hereinafter referred to as SDRAM devices) and asynchronous DRAM devices needed to operate with an operation cycle of 100 MHz or higher.